A Symbolic Technique for the Efficient ATPG of Speed-Independent Circuits
نویسندگان
چکیده
This paper presents a new symbolic ATPG approach for stuck-at faults in speed-independent asynchronous circuits. A closed system is built by composing the circuit model and the specification. Then, a fault is injected in the circuit and the closed system is analyzed by symbolic model checking techniques. The fault is manifested if a discrepancy state is reached. A sequence of events to reproduce the failure in a real circuit is generated during the test application phase. Such sequence is transformed into synchronous test vectors, suitable for commercial testers. The main contribution of this work is the use of the circuit’s specification to efficiently drive the analysis, and the assumption of the fundamental mode of operation in order to reduce the state space required for the analysis and test pattern generation.
منابع مشابه
Improving topological ATPG with symbolic techniques
This paper presents a new approach to Automatic Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to deal with very large circuits, but often fail when highly sequential subnetworks are found. On the other hand, symbolic techniques based on Binary Decision Diagrams proved themselves very efficient on small or medium circuits, no matter their s...
متن کاملATPG and DFT Algorithms for Delay Fault Testing
With ever shrinking geometries, growing metal density and increasing clock rate on chips, delay testing is becoming a necessity in industry to maintain test quality for speed-related failures. The purpose of delay testing is to verify that the circuit operates correctly at the rated speed. However, functional tests for delay defects are usually unacceptable for large scale designs due to the pr...
متن کاملCombining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems
In the past, Symbolic Trajectory Evaluation (STE) has been shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple array blocks together as a single system, the run-time OBDD sizes would often blow up. In this paper, we propose the use of both ATPG-based justification engine and symbolic simulation to facilitate the application of STE proof met...
متن کاملCombinational test generation for various classes of acyclic sequential circuits
It is known that a class of acyclic sequential circuits called balanced circuits can be tested by combinational ATPG. The first contribution of this paper is a modified and efficient combinational single fault ATPG method for any general (not necessarily balanced) acyclic circuit. Without inserting real hardware, we create a “balanced” ATPG model of the circuit in which all reconverging paths h...
متن کاملStudies on Integrating SAT-based ATPG in an Industrial Environment
Due to ever increasing design sizes, more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. Recently, SAT-based approaches for test pattern generation have been shown to be very efficient even on large industrial circuits. But these SAT-based techniques are not always superior to classical ATPG approaches. An integration of SAT-based engines into the classical ATPG flow c...
متن کامل